The present invention relates to electromechanical systems for testing integrated circuit chips (IC-chips).
Typically, a single IC-chip contains between one-hundred-thousand and one-million transistors, and those transistors must be tested before the IC-chip is sold to a customer. Usually, each IC-chip is incorporated into an integrated circuit module (IC-module) before it is tested. In one type of IC-module, the IC-chip is attached to a substrate and covered with a lid. Alternatively, the lid may be left off of the IC-module. In either case, electrical terminals are provided on the substrate which are connected by microscopic conductors in the substrate to the IC-chip.
In the prior art, one method of testing IC-chips was as follows. Initially, a group of IC-modules was manually placed in respective sockets that were mounted on a printed circuit board. The printed circuit board had electrical connectors on one edge of the board; and those connectors would carry test signals, as well as DC electrical power, for the IC-chips in the IC-modules. Several of the above printed circuit boards were provided.
After the IC-modules were placed in the sockets on all of the printed circuit boards, those printed circuit boards were manually inserted into fixed slots in an electromechanical system where the actual testing would occur. As each printed circuit board was inserted into a slot, the electrical connectors on the edge of the board would plug into mating connectors that were provided in the slot.
Usually, each slot had a vertical orientation, and all of the slots were side-by-side in a horizontal row. Multiple signal conductors were provided on a backplane in the system which extended from the connectors in the slots to a test signal generator. This test signal generator sent test signals to the IC-chips and received responses from them. Also, electrical power conductors were provided on the backplane which extended from the connectors in the slots to one or more power supplies.
Often it is desirable to perform “burn-in” tests on the IC-chips wherein the IC-chips are held at a high temperature while electrical power, with or without test signals, is applied to the IC-chips. The high temperature accelerates the occurrence of failures within the IC-chips. In the prior art, the burn-in tests were performed by enclosing the above system in an oven and providing fans in the enclosure which circulate hot air past the IC-modules.
However, one problem with the above prior art system is that the temperature at which the IC-chips are tested cannot be regulated accurately. This inaccuracy is caused, in part, by variations in the temperature and velocity of the air which flows past each of the IC-modules. Also, the inaccuracy is caused by variations in the electrical power which each IC-chip dissipates as it is being tested, and this problem gets worse as the magnitude of the power variations increase.
The above problem is overcome by another more recent prior art system for testing IC-chips which is disclosed in U.S. Pat. No. 6,307,391 by Tustaniwskyj, et al and which is entitled “Pivoting Springy Mechanism That Opens And Closes Pressed Electrical Contacts With A Force That Is Nearly Constant Over A Range Of Closed Positions”. This '391 system is comprised of a “chip holding subassembly” 12, a “power converter subassembly” 13, and a “temperature regulating subassembly” 14. Multiple sets of these three subassemblies 12, 13 and 14 are held by a frame 11. All of these subassemblies are shown in the patent in FIGS. 1A-1C, and 2.
In the '391 system, the testing begins by manually removing all of the chip holding subassemblies 12 from the frame 11. Then, multiple sockets 12b on each chip holding subassembly 12 are manually loaded with a group of IC-modules. Next, all of the chip holding subassemblies 12 are manually placed back into the frame 11 such that each chip holding subassembly 12 lies between one corresponding power converter subassembly 13 and one corresponding temperature regulating subassembly 14. Then, the corresponding subassemblies 12, 13 and 14 are squeezed together by a “pressing mechanism” 15.
While the corresponding subassemblies 12, 13, and 14 are squeezed together, the IC-chips are tested. During this test, electrical power is sent to the IC-chips from the power converter subassembly 13. Also, electrical test signals may be sent to the IC-chips. In either case, the IC-chips are kept at a selectable temperature by the temperature regulating subassembly 14 which contacts the IC-modules to cool and/or heat them via thermal conduction.
After the testing of the IC-chips is complete, the pressing mechanism 15 stops squeezing the subassemblies 12, 13 and 14 together. Then, all of the chip holding subassemblies 12 are manually taken out of the frame 11, and the IC-modules are manually unloaded from the sockets 12b. Thereafter, other groups of IC-modules are tested in the same fashion.
However, a major drawback with the '391 system is that while the IC-modules are being loaded and unloaded into the chip holding subassemblies, the '391 system is not being utilized to actually test any IC-chips. Also, another drawback is that the manual loading and unloading of the IC-modules into the chip holding subassemblies is labor intensive, which is expensive and prone to error. For example, one common error is that a worker will accidentally destroy an IC-chip by failing to take proper precautions for guarding against electrostatic discharge when manually loading/unloading an IC-module from a chip holding subassembly.
To address the above utilization problem, duplicate sets of the chip holding subassemblies can be provided, and one set can be loaded/unloaded with IC-modules while the other set is being used to test IC-chips in the system. But, providing duplicate sets of the chip holding subassemblies 12 doubles their cost. In addition, the '391 system will still not be used to test IC-chips while any one set of the chip holding subassemblies 12 is put into or taken out of the frame 11.
Accordingly, a primary object of the invention which is claimed herein is to provide a novel system for testing IC-chips which overcomes one or more of the above problems.